REDSTONE ARSENAL, Ala. (June 26, 2025) – The future is now, and the airworthiness work performed at the U.S. Army Combat Capabilities Development Command Aviation & Missile Center is having a real-time effect today for Army aviators.
After entering into a Cooperative Research and Development Agreement, or CRADA, with Rockwell Collins, Inc., the Center’s Systems Readiness Directorate Multi-Core Processor Lab is preparing to release the Multi-Core Processors Airworthiness Playbook, or MAP.
The CRADA constructed an easier and more cost-effective path for programs to achieve airworthiness certification and satisfy all necessary requirements for a Multi-Core Processor implementation. It outlined a possible direction to achieve that certification and answered many of the questions programs have on the topics, thereby increasing the likelihood of program success. It also enabled the Multi-Core Processor Lab to share their expertise, facilities, equipment, and intellectual property with the company, collaborating as equal partners.
“CRADAs allow federal laboratories to partner with non-federal entities outside the Federal Acquisition Regulation,” Billy Gentle, chief, Office of Research and Technology Applications at DEVCOM AvMC. “They offer maximum flexibility to meet the lab’s research and development partnering needs within its mission space.”
What they created under the CRADA will answer the challenging transition from powering helicopter technology with single core processors, or SCPs, to multi-core processors, or MCPs, and how those off-the-shelf MCP chips exhibit significant potential for problematic on-chip shared hardware resource contention.
But the guide’s reach will expand beyond the PEO, said Stephen Rochelle, branch chief for Scout/Attack Software Airworthiness.
“This will make its way throughout the entire industry, which is our goal,” Rochelle said. “Companies will have it, competitors to each other will have it and it will make its way across the entire globe.”
Transitioning from a single-core processor to a multi-core processor had a special challenge in the aviation safety world. A multi-core processor integrates multiple independent processing units, each acting as a separate, independent central processing unit capable of fetching, decoding, and executing instructions.
Sharing on-chip hardware resources between cores can cause nondeterministic slowdowns to software execution times on MCP chips. This raises questions about real-time determinism that the team addressed in the guidance. The MAP will provide a guide to adapt how it certifies real-time software deployed to MCP chips.
“One of the things that we track in computer technology is what's called Moore's law,” Rochelle said. “It's named after one of the founders of Intel, and he basically said, processors are going to double in complexity and capability every two years. This pattern held for 50 to 60 years, and for a long time the result was your processor got faster. But around the year 2000 that quit happening. We are now hitting the limits of quantum mechanics, and the speed of light within the processor and you can only go so fast before the electrons don't do what they need to anymore. Technology said, ‘what if you have more than one processor?’ So instead of going faster, we went wider.”
Utilizing multi-core processors in safety critical aviation applications presents a unique set of challenges primarily due to the stringent requirements for determinism, predictability, and certification. While multi-core processors offer significant advantages in terms of performance, size, weight, and power, these benefits come with substantial hurdles. Each of those CPUs needs to be able to execute instructions in exactly the same way.
How did they guarantee that it would execute those instructions the same way? They tried to break it. With the lab’s experienced programmers, one would expect them to throw the most complicated and sophisticated code at the MCP-powered system. But the system was ready for that and challenged them to think outside of the box.
“We developed a memory bomber -- which executes a lot of memory transactions -- very harshly, to try to exploit that memory interference channel that every program is going to hit,” John Ross, MCP-AI Lab manager said. “So, it was jumping around all over the place, creating a random pattern. But we did it in a way that should exploit this interference channel.
“Well, it figured out our pattern. It put in a jump routine that I didn't know about, and it actually ran faster than it did linearly. So that's one of those gotchas that we had fun with. It outsmarted us. We had to go back and create something that it cannot predict.”
The team stressed that while not a standard, the MAP is a process that has proven to yield a high rate of success, and one that ensures the Soldiers will have significantly more computing power to perform their mission.
“This will ripple not just to Army Aviation but to the entire Dept. of Defense,” Rochelle said. “It will move into civil aviation but then it will also move into the safety critical space everywhere else. We're pushing the edge of what's understood on this.”
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The U.S. Army Combat Capabilities Development Command, known as DEVCOM, is Army Futures Command’s leader and integrator within a global ecosystem of scientific exploration and technological innovation. DEVCOM expertise spans eight major competency areas to provide integrated research, development, analysis and engineering support to the Army and DOD. From rockets to robots, drones to dozers, and aviation to artillery – DEVCOM innovation is at the core of the combat capabilities American Warfighters need to win on the battlefield of the future. For more information, visit devcom.army.mil/.
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